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ISL9106
Data Sheet June 29, 2007 FN6509.0
1.2A 1.6MHz Low Quiescent Current High Efficiency Synchronous Buck Regulator
ISL9106 is a 1.2A, 1.6MHz step-down regulator, which is ideal for powering low-voltage microprocessors in compact devices such as PDAs and cellular phones. It is optimized for generating low output voltages down to 0.8V. The supply voltage range is from 2.7V to 5.5V allowing the use of a single Li+ cell, three NiMH cells or a regulated 5V input. 1.6MHz pulse-width modulation (PWM) switching frequency allows using small external components. It has flexible operation mode selection of forced PWM mode and Skip (Low IQ) mode with typical 17A quiescent current for highest light load efficiency to maximize battery life. The ISL9106 integrates a pair of low ON-resistance P-Channel and N-Channel MOSFETs to maximize efficiency and minimize external component count. The ISL9106 offers a typical 215ms Power-Good (PG) timer when powered up. The timer output can be reset by RSI. When shutdown, ISL9106 discharges the output capacitor. Other features include internal digital soft-start, enable for power sequence, overcurrent protection, and thermal shutdown. The ISL9106 is offered in 10 Ld 3mmx3mm DFN package with 0.9mm typical height. The complete converter can occupy less than 1cm2 area.
Features
* High Efficiency Integrated Synchronous Buck Regulator with up to 95% Efficiency * 2.7V to 5.5V Supply Voltage * 17A Quiescent Supply Current in Skip (Low IQ) Mode * 1.2A Guaranteed Output Current * 3% Output Accuracy Over Temperature/Load/Line * Selectable Forced PWM Mode and Skip Mode * Less than 1A Logic Controlled Shutdown Current * 100% Maximum Duty Cycle for Lowest Dropout * Discharge Output Cap when Shutdown * Internal Digital Soft-Start * Peak Current Limiting, Short Circuit Protection * Over-Temperature Protection * Enable, Power Good Function * 10 Ld 3mmx3mm DFN * Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
* Single Li-Ion Battery-Powered Equipment * DSP Core Power
Ordering Information
PART NUMBER (Note) ISL9106IRZ PART MARKING 106Z TEMP. RANGE (C) PACKAGE (Pb-free) PKG. DWG. # L10.3x3C L10.3x3C
* PDAs and Palmtops
Pinout
ISL9106 (10 LD 3X3 DFN) TOP VIEW
-40 to +85 10 Ld 3x3 DFN -40 to +85 10 Ld 3x3 DFN
ISL9106IRZ-T 106Z
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
VIN 1 NC EN PG MODE 2 3 4 5
10 SW 9 PGND 8 SGND 7 FB 6 RSI
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL9106
Absolute Maximum Ratings (Reference to SGND)
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V EN, RSI, MODE, PG . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN + 0.3V SW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.5V to 6.5V FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
Thermal Information
Thermal Resistance (Notes 1, 2) JA (C/W) JC (C/W) 3x3 DFN Package . . . . . . . . . . . . . . 44 5.5 Junction Temperature Range. . . . . . . . . . . . . . . . . .-40C to +125C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Load Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 1.2A Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-40C to +85C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 2. JC, "case temperature" location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications
Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and the typical specifications are measured at the following conditions: TA = +25C, VIN = VEN = VMODE = 3.6V, VRSI = 0V, L = 2.2H, C1 = 10F, C2 = 10F, IOUT = 0A (see the Typical Application Circuit). SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER SUPPLY Undervoltage Lockout Threshold
VUVLO
Rising Falling
2.2 -
2.5 2.4 17 5 0.05
2.7 34 8 2
V V A mA A
Quiescent Supply Current
IVIN
MODE = VIN, no load at the output MODE = SGND, no load at the output
Shut Down Supply Current OUTPUT REGULATION FB Regulation Voltage
ISD
VIN = 5.5V, EN = LOW
VFB
TA = 0C to +85C TA = -40C to +85C
0.784 0.78 -3 1.2
0.8 0.8 0.1 0.2 -
0.816 0.82 3 -
V V A % %/V A
FB Bias Current Output Voltage Accuracy Line Regulation Maximum Output Current COMPENSATION Error Amplifier Trans-conductance SW P-Channel MOSFET ON-Resistance
IFB
VFB = 0.75V VIN = VO + 0.5V to 5.5V, IO = 0A to 1.2A , TA = -40C to +85C VIN = VO + 0.5V to 5.5V (minimal 2.7V)
Design info only
-
20
-
A/V
VIN = 3.6V, IO = 200mA VIN = 2.7V, IO = 200mA
-
0.12 0.16 0.11 0.15 90
0.22 0.27 0.22 0.27

N-Channel MOSFET ON-Resistance
VIN = 3.6V, IO = 200mA VIN = 2.7V, IO = 200mA
N-Channel Bleeding MOSFET On Resistance P-Channel MOSFET Peak Current Limit Maximum Duty Cycle PWM Switching Frequency SW Minimum On Time Soft Start-Up Time fS TA = -40C to +85C MODE = LOW (forced PWM mode) IPK VIN = 5.5V 1.5 1.35 -
2.0 100 1.6 1.1
2.6 1.75 100 -
A % MHz ns ms
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ISL9106
Electrical Specifications
Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and the typical specifications are measured at the following conditions: TA = +25C, VIN = VEN = VMODE = 3.6V, VRSI = 0V, L = 2.2H, C1 = 10F, C2 = 10F, IOUT = 0A (see the Typical Application Circuit). (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER PG Output Low Voltage Delay Time PG Pin Leakage Current Minimum Supply Voltage for Valid PG Signal Internal PGOOD Low Rising Threshold Internal PGOOD Low Falling Threshold Internal PGOOD High Rising Threshold Internal PGOOD High Falling Threshold Internal PGOOD Delay Time EN, MODE, RSI Logic Input Low Logic Input High Logic Input Leakage Current Thermal Shutdown Thermal Shutdown Hysteresis
Sinking 1mA, VFB = 0.7V
150
215 0.01 92 88 110.7 107 50
0.3 275 0.1 94.5 91 113.2 110 -
V ms A V % % % % s
PG = VIN = 3.6V
1.2
Percentage of Nominal Regulation Voltage Percentage of Nominal Regulation Voltage Percentage of Nominal Regulation Voltage Percentage of Nominal Regulation Voltage
89.5 85 108.2 104 -
1.4 Pulled up to 5.5V -
0.1 150 25
0.4 1 -
V V A C C
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ISL9106 Typical Operating Performance
100 95 90 EFFICIENCY (%) 85 80 75 70 65 60 55 50 0 200 400 600 800 LOAD CURRENT (mA) 1000 1200 VIN = 4.2V EFFICIENCY (%) VIN = 5.0V VIN = 3.6V 100 95 90 85 80 75 70 65 60 55 50 0 200 400 600 800 1000 1200 VIN = 3.3V VIN = 5.0V VIN = 2.7V
LOAD CURRENT (mA)
FIGURE 1. EFFICIENY vs LOAD CURRENT (VOUT = 3.3V)
FIGURE 2. EFFICIENCY vs LOAD CURRENT (VOUT = 2.5V)
100 SWITCHING FREQUENCY (MHz) 95 90 EFFICIENCY (%) 85 80 75 70 65 60 55 50 0 200 400 600 800 LOAD CURRENT (mA) 1000 1200 VIN = 5.0V VIN = 2.7V VIN = 3.3V
1.60 TA = +25C 1.55
1.50
TA = +85C
1.45
TA = -40C
1.40 2.7
3.4
4.1 INPUT VOLTAGE (V)
4.8
5.5
FIGURE 3. EFFICIENCY vs LOAD CURRENT (VOUT = 1.8V)
FIGURE 4. SWITCHING FREQUENCY vs INPUT VOLTAGE, (VIN = 3.6V, VOUT = 1.5V, IOUT = 600mA)
30 25 20 15 10 5 0 2.7 QUIESCENT CURRENT (mA) QUIESCENT CURRENT (A) TA = +85C
10 9 8 7 6 5 4 3 2 1 3.4 4.1 INPUT VOLTAGE (V) 4.8 5.5 0 2.7 3.4 4.1 INPUT VOLTAGE (V) 4.8 5.5 TA = +25C TA = +85C
TA = +25C
FIGURE 5. IQ vs VIN (MODE = VIN, VOUT = 1.5V, IOUT = 0)
FIGURE 6. IQ vs VIN (MODE = GND, VOUT = 1.5V, IOUT = 0)
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ISL9106 Typical Operating Performance (Continued)
1.550 2.50000
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1.525 TA = +85C
2.49375
TA = +85C
1.500
TA = +25C
2.48750
1.475 TA = -40C 1.450 2.7 3.4 4.1 INPUT VOLTAGE (V) 4.8 5.5
2.48125 TA = -40C 3.4
TA = +25C
2.47500 2.7
4.1 INPUT VOLTAGE (V)
4.8
5.5
FIGURE 7. VOUT vs VIN (MODE = VIN, VOUT = 1.5V, IOUT = 600mA)
FIGURE 8. VOUT vs VIN (MODE = VIN, VOUT = 2.5V, IOUT = 600mA)
2V/DIV
VSW
2V/DIV
VSW
VOUT 1V/DIV
1V/DIV
VOUT
200mA/DIV 200mA/DIV 5V/DIV IL EN 5V/DIV 200s/DIV
IL EN
200s/DIV
FIGURE 9. SOFT-START TO PWM MODE (VIN = 4.2V, VOUT = 1.6V, IOUT = 500mA)
FIGURE 10. SOFT-START TO SKIP MODE (VIN = 4.2V, VOUT = 1.6V, IOUT = 0.01mA)
VSW 2V/DIV 2V/DIV VOUT (AC COUPLED) 20mV/DIV 20mV/DIV
VSW
VOUT (AC COUPLED)
200mA/DIV
IL 1A/DIV
IL
1s/DIV
1s/DIV
FIGURE 11. STEADY-STATE IN SKIP MODE (VIN = 5.0V, VOUT = 1.8V, IOUT = 35mA)
FIGURE 12. STEADY-STATE IN PWM MODE (VIN = 5.0V, VOUT = 1.8V, IOUT = 1.2A)
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ISL9106 Typical Operating Performance (Continued)
2V/DIV
2V/DIV VSW 50mV/DIV VOUT (AC COUPLED) 20mV/DIV VOUT (AC COUPLED) VSW
200mA/DIV
IL
IL 1A/DIV
4s/DIV
1s/DIV
FIGURE 13. STEADY-STATE IN SKIP MODE (VIN = 5.0V, VOUT = 3.3V, IOUT = 35mA)
VSW
FIGURE 14. STEADY-STATE IN PWM MODE (VIN = 5.0V, VOUT = 3.3V, IOUT = 1.2A)
VSW
2V/DIV 100mV/DIV VOUT (AC COUPLED)
2V/DIV VOUT (AC COUPLED)
100mV/DIV
IL 1A/DIV 1A/DIV
IL
100s/DIV
100s/DIV
FIGURE 15. LOAD TRANSIENT TEST (MODE = VIN = 5.0V; VO = 1.5V; IO = 0.01A~1A)
FIGURE 16. LOAD TRANSIENT TEST (MODE = GND, VIN = 5.0V; VO = 1.5V; IO = 0.01A~1A)
VSW
VSW
2V/DIV
2V/DIV 100mV/DIV VOUT (AC COUPLED)
100mV/DIV
VOUT (AC COUPLED)
IL 1A/DIV 1A/DIV
IL
100s/DIV
100s/DIV
FIGURE 17. LOAD TRANSIENT TEST (MODE = VIN = 3.6V; VO = 1.5V; IO = 0.01A~1A)
FIGURE 18. LOAD TRANSIENT TEST (MODE = GND, VIN = 3.6V; VO = 1.5V; IO = 0.01A~1A)
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ISL9106 Typical Operating Performance (Continued)
VSW VSW
2V/DIV VOUT (AC COUPLED)
2V/DIV VOUT (AC COUPLED)
100mV/DIV
100mV/DIV
IL 1A/DIV 1A/DIV
IL
100s/DIV
100s/DIV
FIGURE 19. LOAD TRANSIENT TEST (MODE = VIN = 5.0V; VO = 2.5V; IO = 0.01A~1A)
FIGURE 20. LOAD TRANSIENT TEST (MODE = GND, VIN = 5.0V; VO = 2.5V; IO = 0.01A~1A)
VSW
VSW
2V/DIV
2V/DIV VOUT (AC COUPLED) 100mV/DIV IL VOUT (AC COUPLED)
50mV/DIV
0.5A/DIV IOUT 0.2A/DIV IL
1A/DIV
100s/DIV
100s/DIV
FIGURE 21. LOAD TRANSIENT TEST (MODE = VIN = 5V; VO = 3.3V; IO = 0.2A~0.4A)
FIGURE 22. LOAD TRANSIENT TEST (MODE = GND, VIN = 5.0V; VO = 3.3V; IO = 0.01A~1A)
Pin Descriptions
VIN
Input supply voltage. Connect a 10F ceramic capacitor to power ground.
PG
215ms timer output. This output is a 215ms delayed powergood signal (PG) for the output voltage when output voltage is within the power-good window. It can be reset by a high RSI signal, then 215ms starts when RSI goes from high to low.
NC
No connect.
MODE
Mode selection pin. Connect to logic high or input voltage VIN for low IQ mode; connect to logic low or ground for forced PWM mode. Do not leave this pin floating.
EN
Enable pin. Enable the device when driven to high. Shut down the chip and discharge output capacitor when driven to low. Do not leave this pin floating.
SW
Switching node connection. Connect to one terminal of inductor.
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ISL9106
PGND
Power ground. Connect all power grounds to this pin.
Exposed Pad
The exposed pad must be connected to the PGND pin for proper electrical performance. The exposed pad must also be connected to as much as possible for optimal thermal performance.
SGND
Analog ground. SGND and PGND should only have one point connection.
FB
Buck regulator output feedback pin. Connect to the output through voltage divider resistor for adjustable output voltage.
RSI
This input resets the 215ms timer. When the output voltage is within the power-good window, an internal timer is started and generates a PG signal 215ms later when RSI is low. A high RSI resets PG and RSI high to low transition restarts the internal counter if the output voltage is within the window, otherwise the counter is reset by the output voltage condition. Do not leave this pin floating.
Typical Applications
INPUT 2.7V TO 5.5V VIN C1 10F ISL9106 SW L 2.2H C2 10 F R2 100k C3 220pF OUTPUT 1.6V/1.2A
NC
PGND
EN R1 100k PG MODE
SGND R3 100k FB RSI
PARTS L C1 C2 C3 R1, R2, R3
DESCRIPTION Inductor Input capacitor Output capacitor Capacitor Resistor
MANUFACTURERS Sumida Murata Murata Murata Various
PART NUMBER CDRH2D14NP-2R2NC GRM21BR60J106KE19L GRM21BR60J106KE19L GRM188R71H221KA01C
SPECIFICATIONS 2.2H/1.50A/75m 10F/6.3V 10F/6.3V 220pF/50V 100k, SMD, 1%
SIZE 3.2mmx3.2mmx1.55mm 2.0mmx1.25mmx1.25mm 2.0mmx1.25mmx1.25mm 1.6mmx0.8mmx0.8mm 1.6mmx0.8mmx0.45mm
FIGURE 23. TYPICAL APPLICATION DIAGRAM
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ISL9106 Block Diagram
MODE
SOFTSTART SHUTDOWN
SHUTDOWN
SLOPE COMP RSI VREF5 FB + SCP
VREF3
+
+ + SKIP PGOOD DELAY
VREF4
PG
Theory of Operation
The ISL9106 is a step-down switching regulator optimized for battery-powered handheld applications. The regulator operates at typical 1.6MHz fixed switching frequency under heavy load condition to allow small external inductor and capacitors to be used for minimal printed-circuit board (PCB) area. At light load, the regulator can be selected to enter skip mode to reduce the switching frequency, unless forced to the fixed frequency, to minimize the switching loss and to maximize the battery life. The quiescent current under skip mode with no loading is typically only 17A. The supply current is typically only 0.1A when the regulator is disabled.
PWM Control Scheme
The ISL9106 uses the peak-current-mode pulse-width modulation (PWM) control scheme for fast transient response and pulse-by-pulse current limiting. Figure 24 shows the circuit functional block diagram. The current loop consists of the oscillator, the PWM comparator COMP,
9
+
EN
BANDGAP
0.8V
EAMP
OSCILLATOR + COMP PWM/PFM LOGIC CONTROLLER PROTECTION DRIVER
VIN
SW
+
PGND
+ CSA + OCP
VREF1
SGND
VREF2 ZERO-CROSS SENSING
FIGURE 24. FUNCTIONAL BLOCK DIAGRAM
current sensing circuit, and the slope compensation for the current loop stability. The current sensing circuit consists of the resistance of the P-Channel MOSFET when it is turned on and the Current Sense Amplifier (CSA). The control reference for the current loops comes from the Error Amplifier (EAMP) of the voltage loop. The PWM operation is initialized by the clock from the oscillator. The P-Channel MOSFET is turned on at the beginning of a PWM cycle and the current in the P-Channel MOSFET starts ramping up. When the sum of the CSA output and the compensation slope reaches the control reference of the current loop, the PWM comparator COMP sends a signal to the PWM logic to turn off the P-Channel MOSFET and to turn on the N-Channel MOSFET. The N-MOSFET remains on till the end of the PWM cycle. Figure 25 shows the typical operating waveforms during the normal PWM operation. The dotted lines illustrate the sum of the slope compensation ramp and the CSA output.
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ISL9106
vEAMP vCSA d iL vOUT
FIGURE 25. PWM OPERATION WAVEFORMS
The output voltage is regulated by controlling the reference voltage to the current loop. The bandgap circuit outputs a 0.8V reference voltage to the voltage control loop. The feedback signal comes from the FB pin. The soft-start block only affects the operation during the start-up and will be discussed separately in "Soft-Start-Up" on page 11. The EAMP is a transconductance amplifier, which converts the voltage error signal to a current output. The voltage loop is internally compensated by a RC network. The maximum EAMP voltage output is precisely clamped to the bandgap voltage.
Once ISL9106 enters the skip mode, the pulse modulation starts being controlled by the SKIP comparator shown in Figure 24. Each pulse cycle is still synchronized by the PWM clock. The P-Channel MOSFET is turned on at the rising edge of clock and turned off when its current reaches 20% of the peak current limit. As the average inductor current in each cycle is higher than the average current of the load, the output voltage rises cycle over cycle. When the output voltage reaches 1.5% above its nominal voltage, the PChannel MOSFET is turned off immediately and the inductor current is fully discharged to zero and stays at zero. The output voltage reduces gradually due to the load current discharging the output capacitor. When the output voltage drops to the nominal voltage, the P-Channel MOSFET will be turned on again, repeating the previous operations. The regulator resumes normal PWM mode operation when the output voltage is sensed to drop below 1.5% of its nominal voltage value.
Enable
The enable (EN) pin allows user to enable or disable the converter for purposes such as power-up sequencing. With EN pin pulled to high, the converter is enabled and the internal reference circuit wakes up first and then the soft start-up begins. When EN pin is pulled to logic low, the converter is disabled, the P-Channel MOSFET is turned off immediately and the output capacitor is discharged through internal discharge path.
Skip Mode
With the MODE pin connected to logic high, ISL9106 enters a pulse-skipping mode at light load to minimize the switching loss by reducing the switching frequency. Figure 26 illustrates the skip mode operation. A zero-cross sensing circuit (as shown in Figure 24) monitors the N-Channel MOSFET current for zero crossing. When it is detected to cross zero for 8 consecutive cycles, the regulator enters the skip mode. During the 8 consecutive cycles, the inductor current could be negative. The counter is reset to zero when the sensed N-Channel MOSFET current does not cross zero during any cycle within the 8 consecutive cycles.
Power Good
The ISL9106 offers a power-good (PG) signal. When the output voltage is not within the power-good window, the PG pin outputs an open-drain low signal. When the output voltage is within the power-good window, an internal powergood signal is issued to turn off the open-drain MOSFET so that PG pin can be externally pulled to high. The rising edge of the PG output is delayed by 215ms (typical) from the time the power-good signal is issued.
8 CYCLES
CLOCK 20% PEAK CURRENT LIMIT IL
0 1.015*VOUT_NOMINAL
VOUT VOUT_NOMINAL
FIGURE 26. SKIP MODE OPERATION WAVEFORMS
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ISL9106
Mode Selection
The MODE pin is provided on ISL9106 to select the operation mode. When it is driven to logic low or ground, the regulator operates in forced PWM mode. Under forced PWM mode, the device remains at the fixed PWM operation (typical at 1.6MHz), regardless of if the load current is high or low. When the MODE pin is driven to logic high or connected to input voltage VIN, the regulator operates in either SKIP mode or fixed PWM mode depending on the different load conditions. maintain the output voltage, the P-Channel MOSFET is completely turned on (100% duty cycle). The dropout voltage under such condition is the product of the load current and the ON-resistance of the P-Channel MOSFET. Minimum required input voltage VIN under this condition is the sum of output voltage plus the voltage drop cross the inductor and the P-Channel MOSFET switch.
Thermal Shut Down
The ISL9106 provides built-in thermal protection function. The thermal shutdown threshold temperature is typical +150C with typical +25C hysteresis. When the internal temperature is sensed to reach +150C, the regulator is completely shut down and as the temperature is sensed to drop to +125C (typical), the ISL9106 resumes operation starting from the soft-start-up.
RSI Signal
The RSI signal is an input signal, which can reset the PG signal. As shown in Figure 24, the power-good signal is gated by the RSI signal. When the RSI is high, the PG signal remains low, regardless of the output voltage condition.
Applications Information
Inductor and Output Capacitor Selection
To achieve better steady state and transient response, ISL9106 typically uses a 2.2H inductor. The peak-to-peak inductor current ripple can be expressed as follows:
VO V O * 1 - --------- V IN I = -------------------------------------L * fS
Overcurrent Protection
The overcurrent protection is provided on ISL9106 when over load condition happens. It is realized by monitoring the CSA output with the OCP comparator, as shown in Figure 24. When the current at P-Channel MOSFET is sensed to reach the current limit, the OCP comparator is trigged to turn off the P-Channel MOSFET immediately.
Short-Circuit Protection
ISL9106 has a Short-Circuit Protection (SCP) comparator, which monitors the FB pin voltage for output short-circuit protection. When the FB voltage is lower than 0.2V, the SCP comparator forces the PWM oscillator frequency to drop to 1/3 of its normal operation frequency.
(EQ. 1)
In Equation 1, usually the typical values can be used but to have a more conservative estimation, the inductance should consider the value with worst case tolerance; and for switching frequency fS, the minimum fS from the "Eletrical Specifications" table on page 2 can be used. To select the inductor, its saturation current rating should be at least higher than the sum of the maximum output current and half of the delta calculated from Equation 1. Another more conservative approach is to select the inductor with the current rating higher than the P-Channel MOSFET peak current limit. Another consideration is the inductor DC resistance since it directly affects the efficiency of the converter. Ideally, the inductor with the lower DC resistance should be considered to achieve higher efficiency. Inductor specifications could be different from different manufacuturers so please check with each manufacturer if additional information is needed. For the output capacitor, a ceramic capacitor can be used because of the low ESR values, which helps to minimize the output voltage ripple. A typical value of 10F/6.3V ceramic capacitor should be enough for most of the applications and the capacitor should be X5R or X7R.
Undervoltage Lockout (UVLO)
When the input voltage is below the Undervoltage Lock Out (UVLO) threshold, ISL9106 is disabled.
Soft-Start-Up
The soft-start-up eliminates the inrush current during the circuit start-up. The soft-start block outputs a ramp reference to both the voltage loop and the current loop. The two ramps limit the inductor current rising speed as well as the output voltage speed so that the output voltage rises in a controlled fashion. At the very beginning of the start-up, the output voltage is less than 0.2V; hence the PWM operating frequency is 1/3 of the normal frequency.
Power MOSFETs
The power MOSFETs are optimized to achieve better efficiency. The ON-resistance for the P-Channel MOSFET is typically160m and the typical ON-resistance for the N-Channel MOSFET is 150m.
Low Dropout Operation
The ISL9106 features low dropout operation to maximize the battery life. When the input voltage drops to a level that ISL9106 can no longer operate under switching regulation to 11
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ISL9106
Input Capacitor Selection
The main function for the input capacitor is to provide decoupling of the parasitic inductance and to provide filtering function to prevent the switching current from flowing back to the battery rail. A 10F/6.3V ceramic capacitor (X5R or X7R) is a good starting point for the input capacitor selection. The switching node of the converter, the SW pin, and the traces connected to this node are very noisy, so keep the voltage feedback trace and other noise sensitive traces away from these noisy traces. The input capacitor should be placed as close as possible to the VIN pin. The ground of the input and output capacitors should be connected as close as possible as well. The heat of the IC is mainly dissipated through the thermal pad. Maximizing the copper area connected to the thermal pad is preferable. In addition, a solid ground plane is helpful for EMI performance.
TABLE 1. ISL9106 CIRCUIT CONFIGURATION vs VOUT (EQ. 2) VOUT (V) 0.8 1.0 1.2 1.5 1.8 2.5 2.8 3.3 L (H) 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 C2 (F) 10 10 10 10 10 10 10 10 R2 (k) 0 44.2 80.6 84.5 100 100 100 102 C3 (pF) N/A 470 270 270 220 220 220 220 R3 (k) 100 178 162 97.6 80.6 47.5 40.2 32.4
Output Voltage Setting Resistor Selection
The voltage divider resistors, R2 and R3, as shown in Figure 23, set the desired output voltage value. The output voltage can be calculated using Equation 2:
R 2 V O = V FB * 1 + ------ R 3
where VFB is the feedback voltage (typically it is 0.8V). The current flowing through the voltage divider resistors can be calculated as VO/(R2 + R3), so larger resistance is desirable to minimize this current. On the other hand, the FB pin has leakage current that will cause error in the output voltage setting. The leakage current has a typical value of 0.1A. To minimize the accuracy impact on the output voltage, select the R3 no larger than 200k. C3 (shown in Figure 23) is highly recommended to be added for improving stability and achieving better transient response. C3 can be calculated using Equation 3:
1 C 3 = ---------------------------------------------------2 x x R 2 x 7.3kHz
(EQ. 3)
Table 1 provides the recommended component values for some output voltage options.
Layout Recommendation
The PCB layout is a very important converter design step to make sure the designed converter works well, especially under the high current high switching frequency condition. For ISL9106, the power loop is composed of the output inductor L, the output capacitor COUT, the SW pin and the PGND pin. It is necessary to make the power loop as small as possible and the connecting traces among them should be direct, short and wide; the same type of traces should be used to connect the VIN pin, the input capacitor CIN and its ground. In order to make the output voltage regulate well and avoid the noise couple from the power loop (especially for SKIP mode operation), the SGND pin should be connected with the PGND pin at the terminals of the load and a star ground connection should be used.
12
FN6509.0 June 29, 2007
ISL9106 Dual Flat No-Lead Plastic Package (DFN)
2X 0.10 C A A D 2X 0.10 C B
L10.3x3C
10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A
E
MIN 0.85 -
NOMINAL 0.90 0.20 REF
MAX 0.95 0.05
NOTES -
A1 A3 b D
6 INDEX AREA
0.20
0.25 3.00 BSC
0.30
5, 8 -
TOP VIEW
B
D2
// 0.10 C 0.08 C
2.33
2.38 3.00 BSC
2.43
7, 8 -
E E2 e k L 0.20 0.35 1.59
A C SEATING PLANE SIDE VIEW A3
1.64 0.50 BSC 0.40 10 5
1.69
7, 8 -
0.45
8 2 3 Rev. 1 4/06
D2 (DATUM B) 1 2 D2/2
7
8
N Nd NOTES:
NX k E2
6 INDEX AREA (DATUM A)
1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd refers to the number of terminals on D. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip.
E2/2 NX L N 8 N-1 NX b e (Nd-1)Xe REF. BOTTOM VIEW C L NX (b) 5 SECTION "C-C" CC e TERMINAL TIP (A1) 9L 5 0.10 M C A B
6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. COMPLIANT TO JEDEC MO-229-WEED-3 except for dimensions E2 & D2.
FOR ODD TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 13
FN6509.0 June 29, 2007

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